1. Field of the Invention
The present invention generally relates to dynamic type semiconductor memory devices and, more specifically, to a bit line structure capable of reducing errors in reading.
FIG. 1 is a block diagram showing the whole structure of a common dynamic type semiconductor memory device (hereinafter referred to as a DRAM).
Referring to the figure, in the memory cell array 1, a plurality of word lines and a plurality of bit line pairs are arranged intersecting with each other, with memory cells provided at respective intersections. The word lines in the memory cell array 1 are connected to a row decoder 3 through a word driver 2. The bit line pairs in the memory cell array 1 are connected to a column decoder 6 through a sense amplifier portion 4 and an I/O switching portion 5. A row address buffer 7 is connected to the row decoder 3, while a column address buffer 8 is connected to the column decoder 6.
In data reading, first, the row address buffer applies an externally applied address signal AD as a row address signal RA to the row decoder 3 in response to an externally applied row address strobe signal RAS. The row decoder 3 selects one of the plurality of word lines in response to the row address signal RA. Consequently, data in the plurality of memory cells connected to the selected word lines are read to respective corresponding bit lines, with the data detected and amplified by the sense amplifier portion 4. Thereafter, the column address buffer 8 applies an externally applied address signal AD as a column address signal CA to the column decoder 6 in response to an externally applied column address strobe signal CAS. The column decoder 6 selects one of the data of one row latched in the sense amplifier portion 4 in response to the column address signal CA. The selected data is externally outputted as an output data D.sub.OUT through the I/O switch portion 5 and through an output buffer 9.
In data writing, an input data D.sub.in is written in a memory cell selected by the row decoder 3 and the column decoder 6 through an input buffer 10 and I/O switch portion 5.
FIG. 2 is a schematic diagram showing a main portion of the memory cell array of the DRAM shown in FIG. 1.
Referring to the figure, a plurality of bit line pairs BL, BL are arranged intersecting with a plurality of word lines WL. Memory cells MC are connected to the intersections between the bit lines BL, BL and the word lines WL. Each memory cell MC comprises a transfer gate TG formed of an N channel MOS transistor and a capacitance Cs storing information of "H" or "L" level. Dummy word lines DWL0, DWL1 are arranged intersecting with the bit line pairs BL, BL. Dummy cells DC0 are provided at intersections between the dummy word line DWL0 and the bit lines BL, while dummy cells DC1 are provided at the intersections between the dummy word line DWL1 and the bit lines BL. An intermediate potential V.sub.cc /2 between the power supply potential V.sub.cc and the ground potential is stored in the dummy cells DC0 and DC1.
A sense amplifier SA is connected to each bit line pair BL and BL. The plurality of word lines WL and the dummy word lines DWL0 and DWL1 are connected to the row decoder 3. The bit line pairs BL and BL are connected to a data input/output line pairs I/O and I/ through transfer gates Q1 and Q2 which are formed of N channel MOS transistors. The transfer gates Q1 and Q2 have their gates connected to the column decoder 6.
In data reading, one word line WL is selected by the row decoder 3, with the potential thereof raised to the "H" level. Consequently, the data in the memory cells MC connected to the word line WL are respectively read to the corresponding bit line BL or BL. If the data are read to the bit lines BL, for example, the potential of the dummy word line DWL1 is raised to the "H" level, and the potential of the dummy cells DC1 is read to corresponding bit lines BL. Consequently, the potential of the bit lines BL becomes the reference potential. Meanwhile, the potential of the bit lines BL, from which data have been read, becomes a little higher or lower than the reference potential. Thereafter, the potential difference between the bit line pairs BL and BL is amplified by a sense amplifier SA. Any one set of the transfer gates Q1 and Q2 is turned on by the column decoder 102, and the data on the bit line pair BL and BL connected thereto are read on the data input/output line pair I/O and I/ .
Now, the potential which appears on each bit line pair BL, BL in data reading will be discussed.
FIG. 3 is a schematic diagram showing capacitance generated on each bit line.
As is shown in the figure, a capacitance C.sub.1 exists between each bit line and the ground potential (fixed potential) through a cell plate or a substrate; a bit line capacitance C.sub.2 exists between the bit lines constituting a pair; and a bit line capacitance C.sub.3 exists between adjacent bit line pairs. The cell capacitance of the memory cell MC is represented by C.sub.S. Each of the bit lines has the length of l.
When the "H" level data is stored in a memory cell by V.sub.cc writing, the charges stored in the memory cell will be C.sub.S V.sub.cc. Meanwhile, when the "L" level data is stored in the memory cell by OV writing, the charges stored in the memory cell will be 0. Charges C.sub.S V.sub.cc /2 (b V.sub.cc /2 writing) are stored in the dummy cells DC0 and DC1. It is assumed that the bit line pairs are precharged to the supply potential V.sub.cc prior to the reading operation.
Now, let us consider a case in which a memory cell connected to the bit line BL1 is selected and a dummy cell is connected to the bit line In that case, the potential V.sub.BL1 of the bit line BL1 and the potential V.sub.BL1 of the bit line BL1 be represented by the following equation. Namely, the potential V.sub.BL1 of the bit line BL1 when the "L" level data is read from the selected memory cell will be represented by the following equation. ##EQU1## The potential V.sub.BL1 of the bit line BL1 when the "H" level data is read from the selected memory cell will be represented by the following equation. ##EQU2## The potential V.sub.BL1 the bit line BL1 will be represented by the following equation. ##EQU3## Where .DELTA.V.sub.BL0, .DELTA.V.sub.BL1, .DELTA.V.sub.BL1 and .DELTA.V.sub.BL2 are changes of the potential on the respective bit lines represented by the indices.
In consideration of the fact that the precharge level of the bit line BL1 is the same as that of the bit line BL1, that voltage difference between the bit lines constituting a pair will be represented by the following equation, derived from the operation of (1)-(3) and (2) -(3): ##EQU4## Where ##EQU5##
In the equation (4), the "+" of the double sign corresponds to the reading of the "H" level data, while "-" corresponds to the reading of the "L" level data. The first term of the right side of the equation (4) is the original reading voltage difference, and the second term is a noise component applied through the coupling capacitance from the bit line BL0 of the adjacent bit line pair and the bit line BL2 of another adjacent bit line pair.
Meanwhile, when the bit line pitch becomes smaller and smaller as the degree of integration of the memory cell becomes higher and higher, the capacitance C.sub.3 between the bit line pair is increased, and the second term of the right side of the equation (4) becomes larger and larger. Consequently, the reading voltage is reduced, whereby the reading margin is decreased and the soft error rate is increased, causing malfunctions.
In order to solve the above described problem, the inventors of the present invention have proposed a semiconductor memory device in which the degradation of the reading voltage amplitude caused by the noise derived from the bit line capacitance between adjacent bit line pairs can be made 0 (see "Bit Line Structure for Semiconductor Memory Device" which was mentioned as the related co-pending application).
The structure of the proposed semiconductor memory device will be described with reference to FIG. 4.
As shown in FIG. 4, each of the bit line pairs BL0, BL0,BL1,BL1, . . . is divided into 4 sections a, b, c and d each having the length of l/4, and the bit lines of the bit line pair intersect with each other at the points CP1, CP2 and CP3 of division, in the following manner.
(1) The bit lines BL0 and BL0 intersect with each other at the point CP2.
(2) The bit lines BL1 and BL1 with each other at the points CP1 and CP3.
(1)' The bit lines BL2 and BL2 intersect with each other at the point CP2.
(2)' The bit lines BL3 and BL3 intersect with each other at the points CP1 and CP3.
Namely, counting from the bit line pair BL0 and BL0, the bit lines of the odd-numbered bit line pair intersect with each other at the point CP2, while the bit lines of the even-numbered bit line pair intersect with each other at the points CP1 and CP3. Therefore, the capacitive coupling noise derived from adjacent bit line pairs to each bit line pair will be represented by the following equations, when it is considered in the same manner as the prior art of FIG. 3. (1) The capacitive coupling noise V.sub.BL1, and V.sub.BL1 to the bit lines BL0 and BL0 from adjacent bit lines will be represented by the following equation. ##EQU6##
The bit line BL1 receives the noise .DELTA.V.sub.BL0 in the section a, the noise .DELTA.V.sub.BL2 in the section b, the noise .DELTA.V.sub.BL2 in the section c, and the noise .DELTA.V.sub.BLO the section d, respectively. The bit line BL1 receives the noise .DELTA.V.sub.BL2 in the section a, the noise .DELTA.V.sub.BL0 the section b, the noise .DELTA.V.sub.BL0 in the section c, and the noise .DELTA.V.sub.BL2 in the section d, respectively. Therefore, the capacitive coupling noise .DELTA.V.sub.BL1 and the .DELTA.V.sub.BL1 are exactly equal to each other.
(2) The capacitive coupling noise .DELTA.V.sub.BL2, and to the bit lines BL2 and BL2 from adjacent bit line pairs will be represented by the following equation. ##EQU7##
The bit line BL2 receives the noise .DELTA.V.sub.BL1 the section a, the noise .DELTA.V.sub.BL1 in the section b, the noise .DELTA.V.sub.BL3 in the section c, and the noise .DELTA.V.sub.BL3 in the section d, respectively. The bit line BL2 receives the noise .DELTA.V.sub.BL3 in the section a, the noise .DELTA.V.sub.BL3 in the section b, the noise .DELTA.V.sub.BL1 in the section c, and the noise .DELTA.V.sub.BL1 in the section d, respectively. Therefore, the capacitive coupling noise .DELTA.V.sub.BL2, is exactly equal to the noise .DELTA.V.sub.BL2.
In the same manner, the capacitive coupling noise received by each of the bit lines of the bit line pairs from adjacent bit line pairs will be the same in all of the bit line pairs.
(3) The capacitive coupling noise .DELTA.V.sub.BL0 and .DELTA.V.sub.BL0 to the bit lines BL0 and BL0 at the end portions of the memory array will be represented by the following equation. ##EQU8##
The bit line BL0 receives the noise .DELTA.V.sub.BL1 in the section c, and the noise .DELTA.V.sub.BL1 in the section d. The bit line BL0 receives the noise .DELTA.V.sub.BL1 in the section a, and the noise .DELTA.V.sub.BL1 the section b. Therefore, the capacitive coupling noise .DELTA.V.sub.BL0, is exactly equal to the noise .DELTA.V.sub.BL0.
As described above, in the semiconductor memory device of FIG. 4, the capacitive coupling noise to each of the bit lines constituting bit line pairs from adjacent bit line pairs will be the same in reading signals from memory cells. Therefore, the reduction of the reading voltage difference derived from the capacitive coupling noise can be eliminated, whereby the reading margin is enlarged and the soft error ratio can be reduced.
In such semiconductor memory devices, each of the intersections provided at the points CP1, CP2 and CP3 can not be laid out in perfect symmetry with regard to the bit line pair.
FIG. 5 is a plan view showing the intersecting portions of the bit lines, and FIG. 6 is a cross sectional view taken along line VI--VI of FIG. 5.
Referring to both figures, an oxide film 28 for isolation defining an active region is formed on a main surface of a semiconductor substrate 25. In the active region, impurity regions 29a and 29b defining a transistor and a capacitor region of a memory cell are formed. A cell plate 27 defining the capacitor is formed above the impurity region 29b with an insulating film interposed therebetween. An interlayer insulating film 30 is formed covering entirely over the main surface of the semiconductor substrate 25. A word line 21 controlling conduction of the memory transistor of the memory cell is formed in the interlayer insulating film 30. A bit line 22 is formed on the interlayer insulating film 30 in a direction orthogonal to the word line 21. The bit line 22 is connected to the impurity region 29a through a contact hole 23 formed on the interlayer insulating film 30. The bit line 22 is formed of aluminum interlayer and the like. At the lower bit line of the intersecting portion of the bit line pair, the aluminum interlayer is connected to a polysilicon interlayer 24 through a contact 26.
As is apparent from the above described structure, at the intersecting point of the bit line pair, the material of one bit line is different from the other bit line. Therefore, the value of the capacitance C.sub.1 shown in FIG. 3 at this portion is different in each bit line. Consequently, the reading voltage difference between each of the bit lines is degraded, whereby the decrease of the soft error ratio is not fully accomplished. Namely, the bit lines viewed as a whole do not have a well balanced layout. In consideration of the balance between the bit line pairs, the inventors of the present invention have proposed a semiconductor memory device such as shown in FIG. 7 (see "Bit Line Structure for Semiconductor Memory Device" which was mentioned as the related co-pending application).
The semiconductor memory device of FIG. 7 is different from that of FIG. 4 in that additional intersecting portions are provided at the point CP4 near the end portion of the bit lines in the odd-numbered bit line pairs BL0, BL0, BL2, BL2 . . . .
In the semiconductor memory device of FIG. 7, each of the even-numbered bit line pairs BL1, BL1, BL3, BL3, . . . has two intersecting portions. Therefore, a well-balanced layout can be provided for the bit line pairs, when viewed as a whole. If the bit line is formed of Al layer and the wiring layer which can intersect therewith is formed of polysilicon layer, the bit line BL1 should be formed of Al and the bit line BL1 should be formed of polysilicon at the intersection of the point CP1, while the bit line BL1 should be formed of polysilicon and the bit line BL1 should be formed of Al at the intersection of the point CP3. By doing so, the capacitance C.sub.1 of the bit line pairs becomes equal to each other, whereby the imbalance of the stray capacitance can be avoided. In the semiconductor device of FIG. 7, a dummy intersecting point is added at the point CP4 so that the capacitance of the odd-numbered bit line pairs will be balanced, for the same purpose. Consequently, capacitances for all bit lines can be balanced.
In the semiconductor memory devices of FIGS. 4 and 7, the bit line pairs are divided into four sections, and each of the bit lines constituting a pair intersect with each other at appropriate positions. The number of sections may be an integer multiple of 4 such as 8, 12 and so on to provide the same effect. FIG. 8 shows an example in which the bit lines are divided into 8 sections In the example of FIG. 8, the structure of FIG. 7 is repeated twice It is apparent that the example of FIG. 8 provides the same effect as that of FIG. 7.
However, even in the structures of the bit line pairs shown in FIGS. 7 and 8, the capacitive coupling noise of respective bit line pairs is not equal to each other in the strict sense. The reason for this is that the capacitive coupling noise is generated in the small portion between the point CP4 and the sense amplifier SA, preventing well-balanced layout of the bit line pairs.